Field of the Invention
The present invention relates to a semiconductor device having a through electrode and a manufacturing method of the semiconductor device.
Description of the Related Art
A semiconductor device (semiconductor chip) such as a solid state imaging device has the structure including a semiconductor substrate on which elements such as a transistor are formed, an insulating member arranged on the semiconductor substrate, and wiring portions arranged therein, for example. The wiring portion includes a wiring pattern connecting one element to another, a wiring pattern used for supplying electrical power to an element, and the like. Further, the semiconductor device further includes an electrode portion used for connecting the semiconductor device to an external device (another semiconductor device, a circuit substrate, or the like). A part of the wiring portion may be connected to the electrode portion.
When a semiconductor device is connected to an external device by using a flip-chip connection, for example, an electrode portion called a bump is used. Some electrode portions as discussed above may be formed from a back surface side (the opposite side to the wiring portion of the semiconductor substrate) of the semiconductor substrate to the wiring portion. Since such an electrode portion is formed so as to penetrate the semiconductor substrate (for example, a silicon substrate), the electrode portion may be called “through electrode”.
Japanese Patent Application Publication No. 2011-40457 discloses a process of fabricating a Through Silicon Via (TSV) that is a through electrode.
The through electrode described above is formed as follows, for example. That is, first, a via hole is formed by etching a semiconductor substrate from the back surface side thereof and removing a part of the semiconductor substrate and a part of a wiring insulating member to expose a part of the wiring portion (a part to be connected to an external device). Next, an insulating film is formed on the back surface of the semiconductor substrate and the inner surface of the via hole. Next, a through electrode is formed by embedding a conductive member in the via hole.
One of the schemes of forming a vertical via hole so as to penetrate from the back surface side of a semiconductor substrate may be a so-called Bosch process. Basically, the Bosch process is a process of gradual etching in the vertical direction by repeating a cycle of three steps of (1) an isotropic etching step, (2) a protection film deposition step, and (3) a protection film removal step at the via bottom. As a structural feature of the inner wall of a through hole formed by the Bosch process, a concave-convex shape called a scallop occurs. As this scallop is covered with an insulating film, there is a problem of a crack (break) occurring inside the insulating film starting from a convex portion of the scallop. Such a crack may cause a reduction in the dielectric voltage of the insulating film.
Japanese Patent Application Publication No. 2011-40457 discloses that a silicon oxide film is formed by using a microwave excitation plasma Chemical Vapor Deposition (CVD) method in order to obtain an insulating film having a good film quality as an insulating film formed on the inner wall of a hole formed in the semiconductor substrate. Further, Japanese Patent Application Publication No. 2011-40457 discloses that a multilayered insulating film comprising silicon oxide films and silicon nitride films is formed. Even when a multilayered insulating film is formed, however, if a crack starting from a scallop occurs after the final insulating film is deposited, the crack will be formed continuously inside the multilayered insulating film from the bottom surface on the semiconductor substrate side to the top surface on the through electrode side. As a result, the dielectric voltage of the insulating film decreases, which may lead to a problem of a reduction in the yield rate or a reduction in the long-term reliability due to a short-circuit.